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HW/SW Co-simulation solution for Zynq SoC based systems using Riviera-PRO and QEMU

With the rise of heterogeneous architecture, the HW/SW co-verification has become a new challenge for verification engineers. Xilinx Zynq device is an ever-growing SoC which consists of ARM processor and FPGA programmable logics. While using this device, an application will be running on the ARM processor and the hardware IPs will be placed in the FPGA side. So, using the typical logic simulator is not going to be enough to verify the entire SoC. Aldec provides a HW/SW Co-Simulation interface between Riviera-PRO and Xilinx Quick Emulator QEMU. System integration and Co-Simulation of HDL code with software applications/drivers executing in QEMU is now simplified with full compilation SystemC to library (LibSysytemCTLM-SoC). It is executed under Riviera-Pro simulator. The LibSysytemCTLM-SoC shares Remote Port to connect Riviera-PRO and QEMU, and converts SystemC TLM transactions to AXI and vice versa providing a fast interface for Co-Simulation. In this video, we show you how to easily verify your Xilinx Zynq SoC based designs using Riviera-Pro and Xilinx QEMU. You can read the app note in the link below: https://www.aldec.com/en/support/reso... Aldec Github: https://github.com/aldec/TySOM-QEMU