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Processing-in-memory in High Bandwidth Memory Architecture with Efficient and Low Latency Channel

In this paper, we propose a processing-in-memory in high bandwidth memory (PIM-HBM) architecture for high bandwidth systems. The main concept is to embed processing units into a logic layer of high bandwidth memory (HBM). The proposed architecture decreases the energy consumption and latency of interconnections. To verify the proposed architecture, we designed on-chip and on-interposer I/O channels using a CMOS 0.18 μm process. We extracted channel parasitic using an electromagnetic (EM) solver and performed a SPICE simulation. As a result, the performance of the proposed PIM-HBM architecture is successfully verified by reducing energy consumption and latency of interconnections by 77 % and 79 % compared to the conventional HBM system. (2019 EPEPS conference)